Hudson River Trading
Design Verification (DV) Engineer - 2027 Grads
Eligibility
- Bachelor’s degree, new graduate (2027)
Graduate-level role in hardware design verification for FPGA/ASIC systems supporting low latency trading, focusing on testbench creation, debugging, and verification environment development.
Responsibilities
- Create testbenches and verification tests for hardware platform
- Write verification plans
- Root-cause RTL bugs
- Collaborate with hardware designers
- Manage test suites and continuous integration
- Develop and improve open-source and internal tools
Requirements
- Bachelor’s degree in computer engineering, computer science or related field
- Experience with RTL functional verification
- Proficiency in Python
- Comfortable with Linux environment
- Familiarity with Cocotb preferred
- C++ experience is a plus
Skills
- Python
- RTL verification
- Linux
- Testbench development
- C++
- Employer posted
- Last checked