Virtu Financial
2027 Internship - FPGA Engineer
Eligibility
- Student status with graduation year 2028
An FPGA engineering internship at Virtu Financial focusing on hardware design lifecycle for low-latency trading systems, offering hands-on experience in FPGA and ASIC solutions with mentoring and real project work.
Responsibilities
- Work across full design lifecycle of FPGA and ASIC solutions from architecture to live hardware bring-up
- Tackle engineering challenges to keep trading systems competitive
- Participate in training and mentorship throughout the internship
- Develop real projects and deliver tangible silicon-based results
Requirements
- Academic background in Electrical or Computer Engineering
- Experience with Hardware Description Languages (SystemVerilog, Verilog)
- Experience working with FPGA vendor tools such as Vivado or Quartus
- Comfortable with software programming languages like Python, C++ or similar
- Strong problem solving and communication skills
- Graduating year of 2028
Graduation requirements
Graduation year: 2028
Skills
- SystemVerilog
- Verilog
- Vivado
- Quartus
- Python
- C++
- problem solving
- communication
- Employer posted
- Last checked